The subject system and method are generally directed to computationally optimizing the characterization process for a logic cell modeling an electronic circuit. More specifically, the subject system and method reduce the processing load, hence the processing time, for characterizing such a logic cell. The system and method provide measures for simplifying the logical representation of nodes within even complex logic cells having multiple logic components in such manner that only electrically relevant nodes are maintained in the representation. This makes for streamlined logical representations of logic cells and obviates extraneous analyses in the mapping of relevant nodes to their appropriate logic levels during a cell characterization process.
Cell characterization processes are known in the art. U.S. Pat. Nos. 8,160,858 and 7,937,256 provide an example. During cell characterization, electrical and logical behavior is extracted from transistor level circuits for logic gate cells into abstract models of timing, power, noise, and logic function. Such cell characterization processes are notoriously computation-intensive and tend to be prohibitively so for cells of some complexity. While various measures have been employed in the art to enhance efficiency, significant inefficiencies remain in cell characterization processes heretofore known.